A seminar was held recently in Pune to update engineering college faculty groups about the latest trends and technologies in the field of Very Large Scale Integration (VLSI) design. The seminar intended to discuss how educational institutions can help to bridge the demand-supply gap of “design aware” talent in the semiconductor industry.
Organised by Cadence Design Systems (India), the seminar provided faculty members with key insights in the VLSI design, bringing in best-in-class technology to educational institutions in Pune. It also provided a platform for the teaching fraternity to exchange views and discuss new ideas.
The seminar was an initiative of the Cadence University Programme (CUP) which now has more than 350 institutes enrolled across India, including IITs, NITs and private engineering colleges.
Speaking about the CUP, Jaswinder Ahuja, corporate vice president and managing director, Cadence Design Systems said, “The semiconductor industry is facing a demand-supply gap of “design aware” talent, coming out of engineering colleges. CUP aims at narrowing this gap. The programme encompasses not just access to best-in-class software, but also faculty development; encouraging innovation among the students through the Cadence Design Contest and preparing them to enter the industry through the Cadence VLSI Certification Programme.”
The seminar also included practical demonstration session to show the breadth and depth of the Cadence technology offerings. “This University seminars are important because they provide the engineering faculty an opportunity to update themselves on the latest trends in VLSI design and share ideas,” said Ahuja.
Cadence Design Systems enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics.
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